3D stacked DRAM is a DRAM having multiple-layer DRAM stacked on and interconnected with each other.
Wide I/O Mobile DRAM
Wide I/O 1&2
See main article Wide IO.
Wide I/O Mobile DRAM uses chip-level 3D stacking with TSV interconnects and memory chips directly stacked upon a SoC.
See main article 3D-SWIFT.
Zhang et al. reorganized the Wide I/O DRAM core in their proposed 3-D SWIFT architecture, which employs a large number of small banks to enable greater bank-level parallelism.
See main article 3-D WiRED.
3-D WiRED is a optimized Wide I/O DRAM architecture, aiming to reduce access latency and energy consumption.
High Bandwidth Memory (HBM)
See main article HBM.
Hybrid Memory Cube (HMC)
See main article HMC.
See main article 3D-Wiz.
3D-Wiz is a high bandwidth, low latency, optically interfaced 3D DRAM architecture with fine grained data organization and activation.
3D-ProWiz is a high-bandwidth, energy-efficient, optically-interfaced 3D DRAM architecture with fine grained data organization and activation.
TSV-based 3D Stacked DDR4 DRAM
- T. Zhang, C. Xu, K. Chen, G. Sun, and Y. Xie, “3D-SWIFT: a high-performance 3D-stacked wide IO DRAM,” (Best Paper Award) in ACM Great Lakes Symposium on VLSI, 2014, pp. 51–56, Houston, TX. Available: http://dx.doi.org/10.1145/2591513.2591529