3D FPGA

www.3dic.org/3D FPGA

Performance of FPGAs can be boosted dramatically by 3D integration in three key metrics: logic density, speed, and power. The major categories of 3D FPGAs are 2.5D FPGAs, stacked 3D FPGAs, and monolithic 3D FPGAs.

Xilinx Virtex-7 2.5D Interposer-based FPGAs

The Xilinx 2.5D FPGAs from the Virtex-7 family fabricated by TSMC using the CoWoS technology are the first commercially available silicon interposer-based FPGAs.

The FPGA is composed of four identical dice arranged such that the vertical routing crosses between the dice. Each horizontal edge of each die has 280 groups of 48 length-12 wires crossing the interposer, which sums to a total of 13440 wires between dice. There are also 40 clock wires crossing the interposer. The average number of wires per vertical channel of this FPGA is 210 and there are approximately 280 vertical channels on the FPGA, resulting in approximately 58800 vertical wires crossing a horizontal cutline within a die. Hence the number of wires which cross the interposer is about 23% of the total number of within-die vertical wires. The 28nm dies are connected to the 65nm silicon inter- poser through microbumps with a 45μm pitch. Hence the area occupied by microbumps at one edge of one die is 13440 × (45μm)2 = 27mm2. Assuming each die is 7 × 12 mm, the bumps have to be spread out near the edge and need to go as far as 2.25mm away from the edge of the die. This greater distance from the border increaes the length of the inter-die connections, and along with the presence of the micro-bumps and their capacitance, leads to an increased delay for these crossing wires vs. that of a typical on-die routing wire. Chaware et al. state that the latency to cross the interposer is approximately 1ns [1]. For comparison, a typical medium length 28 nm FPGA routing wire (e.g. spanning four logic blocks) has a delay of approximately 125 ps, while a longer wire (e.g. spanning 12 logic blocks) has a delay of approximately 250 ps.

Overall, these interposer-based FPGAs have increased delay and reduced connectivity between dies, with approximately 23% of the usual number of vertical wires crossing between dies and approximately 1ns of increased delay to cross the interposer.[2]

Altera 2.5D FPGA with EMIB and HBM DRAM

Altera has launched the Stratix 10 FPGA which consists of HBM2 3D DRAM combined with FPGAs by using the embedded multi-die interconnect bridge (EMIB).

3D FPGA with Stacked TFT SRAM memory

In 2010, T. Naito et al. at Toshiba Corporation presented a 3D FPGA with monolithically integrated thin-film-transistor (TFT) SRAM configuration circuits over 90nm 9 layers of Cu interconnect CMOS successfully fabricated at 300mm LSI mass production line.[3]

3D FPGA with stacked RRAM memory

In 2012, Y. Y. Liauw et al. presented a 3D FPGA with monolithically stacked configuration memory based on the resistive random access memory (RRAM) technology.[4][5]

Reviews

PhD Studies

  • Y. F. Yang Liauw, “Nonvolatile monolithic three-dimensional field programmable gate array with stacked resistive configuration memory,” Ph.D. dissertation, Stanford University, 2012.


Books

  • V. Pangracious, Z. Marrakchi, and H. Mehrez, Three-dimensional design methodologies for tree-based FPGA architecture. 2015. ISBN 978-3-319-19174-4.


References

  1. R. Chaware, K. Nagarajan, and S. Ramalingam. Assembly and Reliability Challenges in 3D Integration of 28nm FPGA Die on a Large High Density 65nm Passive Interposer. In IEEE Electronic Components and Technology Conference (ECTC), pages 279–283, 2012.
  2. CAD and Routing Architecture for Interposer-Based Multi-FPGA Systems. http://www.eecg.utoronto.ca/~vaughn/papers/fpga2014_interposer.pdf
  3. T. Naito, T. Ishida, T. Onoduka, M. Nishigoori, T. Nakayama, Y. Ueno, Y. Ishimoto, A. Suzuki, W. Chung, R. Madurawe, S. Wu, S. Ikeda, and H. Oyamatsu, “World’s first monolithic 3D-FPGA with TFT SRAM over 90nm 9 layer Cu CMOS,” in 2010 Symposium on VLSI Technology, 2010, pp. 219–220. Available: http://dx.doi.org/10.1109/VLSIT.2010.5556234
  4. Y. Y. Liauw, Z. Zhang, W. Kim, A. E. Gamal, and S. S. Wong, “Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory,” in 2012 IEEE International Solid-State Circuits Conference, 2012, pp. 406–408. Available: http://dx.doi.org/10.1109/ISSCC.2012.6177067
  5. Y. F. Yang Liauw, “Nonvolatile monolithic three-dimensional field programmable gate array with stacked resistive configuration memory,” Ph.D. dissertation, Stanford University, 2012.