www.3dic.org/3D NAND

3D NAND is a type of 3D memory with 3D stacked NAND cell layers.

State of the Art

The most popular 3D NAND solutions are vertical-channel (VC) and vertical-gate (VG). In VC gate-all-around type, the channel is realized by etching a hole through the layers stack in one single step, and then forming the transistor structure with deposition of its ONO charge trapping layers, tunnel oxide and the polysilicon channel fill in the middle. The cell gates are constituted by the polysilicon horizontal layer surrounding the vertical channel forming a Gate-All-Around (GAA) structure. The string current flows in the cells in the vertical direction. In the VG-type the vertical etching is necessary to separate the strings in one direction and to separate the wordlines in the other direction. The current flows in horizontal direction and each layer must be connected to the top metal bitlines and source lines by a proper connecting structure.

The NAND Flash Roadmap Summary shows the expected rollout times for NAND flash process nodes of the largest manufacturers compared to the ITRS timeline.


Announcement Date Stacked layers Capacity per chip Company Technology String (channel) orientateon Cell transistor Process sequence
2006 (IEDM2006[1]) 2 - Samsung S3 (Single-crystal Si layer Stacking) technology
2007 (VLSI2007[2]) - - Toshiba BiCS Vertical SONOS GAA Gate first
2009 (VLSI2009[3]) 16 32Gb, test chip Toshiba P-BiCS
2009 (VLSI2009[4]) - - Samsung TCAT (Terabit Cell Array Transistor) Vertical TANOS GAA Gate last
2009 (VLSI2009[5]) - - VSAT (Vertical-Stacked-Array-Transistor) Vertical SONOS planar Gate first
2009 (VLSI2009[6]) - - VG-NAND Horizontal SONOS DG Gate last
2010 (IEDM2010[7]) - - SK Hynix DC-SF (Dual Control gate with Surrounding Floating gate) Vertical FG GAA Gate first
2011 (IMV2011[8]) - - Tohoku University S-SCG (Separated-Sidewall Control Gate) Vertical FG GAA Gate first
2013 August 24 128Gb, 2b/cell, mass product Samsung V-NAND Gen 1
2014 August 32 128Gb, 3b/cell, mass product Samsung V-NAND Gen 2
2014 24 Prototype SK Hynix, Prototype
2015[9] 48 256Gb, 3b/cell, mass product Samsung V-NAND Gen 3
2015 36 128Gb, 2b/cell SK Hynix
2015 March (IEMD2015[10]) 32 256Gb, 2b/cell;

384Gb, 3b/cell

2015 March 48 128Gb, 2b/cell;

256Gb, 3b/cell

Toshiba/SanDisk BiCS2
2015 Toshiba TSV-based 3D stacking
2015 August 48 256Gb, 3b/cell SK Hynix
2016 (ISSCC2016[11]) 32 512Gb, 2b/cell;

768Gb, 3b/cell (4.29Gb/mm2)

Micron/Intel 3D floating gate
2016 July 64 256Gb 3b/cell Toshiba/WDC BiCS3
2016 Aug 64 256Gb 3b/cell Samsung V-NAND Gen 4

3D vertical-gate NAND

3D NAND based on TSVs

On Aug. 6, 2015, Toshiba Corporation announced the development of the world’s first 16-die (max.) stacked NAND flash memory utilizing through-silicon vias (TSVs) technology. The prototype was shown at Flash Memory Summit 2015 held from August 11 to 13 in Santa Clara, USA.[12] Toshiba’s TSV technology achieves an I/O data rate of over 1Gbps with a low voltage supply: 1.8V to the core circuits and 1.2V to the I/O circuits and approximately 50% (compared with Toshiba’s current products.) power reduction of write operations, read operations, and I/O data transfers.


  1. S. M. Jung, J. Jang, W. Cho, H. Cho, J. Jeong, Y. Chang, J. Kim, Y. Rah, Y. Son, J. Park, M. S. Song, K. H. Kim, J. S. Lim, and K. Kim, “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node,” in 2006 International Electron Devices Meeting, 2006, pp. 1–4. Available: http://dx.doi.org/10.1109/IEDM.2006.346902
  2. H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, M. Sato, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, and A. Nitayama, “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,” in 2007 IEEE Symposium on VLSI Technology, 2007, pp. 14–15. Available: http://dx.doi.org/10.1109/VLSIT.2007.4339708
  3. R. Katsumata, M. Kito, Y. Fukuzumi, M. Kido, H. Tanaka, Y. Komori, M. Ishiduki, J. Matsunami, T. Fujiwara, Y. Nagata, L. Zhang, Y. Iwata, R. Kirisawa, H. Aochi, and A. Nitayama, “Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices,” in 2009 Symposium on VLSI Technology, 2009, pp. 136–137.
  4. J. Jang, H. S. Kim, W. Cho, H. Cho, J. Kim, S. I. Shim, Younggoan, J. H. Jeong, B. K. Son, D. W. Kim, Kihyun, J. J. Shim, J. S. Lim, K. H. Kim, S. Y. Yi, J. Y. Lim, D. Chung, H. C. Moon, S. Hwang, J. W. Lee, Y. H. Son, U. I. Chung, and W. S. Lee, “Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory,” in 2009 Symposium on VLSI Technology, 2009, pp. 192–193.
  5. J. Kim, A. J. Hong, S. M. Kim, E. B. Song, J. H. Park, J. Han, S. Choi, D. Jang, J.-T. Moon, and K. L. Wang, “Novel Vertical-Stacked-Array-Transistor (VSAT) for ultra-high-density and cost-effective NAND Flash memory devices and SSD (Solid State Drive),” in 2009 Symposium on VLSI Technology, 2009, pp. 186–187.
  6. W. Kim, S. Choi, J. Sung, T. Lee, C. Park, H. Ko, J. Jung, I. Yoo, and Y. Park, “Multi-layered Vertical Gate NAND Flash overcoming stacking limit for terabit density storage,” in 2009 Symposium on VLSI Technology, 2009, pp. 188–189.
  7. S. Whang, K. Lee, D. Shin, B. Kim, M. Kim, J. Bin, J. Han, S. Kim, B. Lee, Y. Jung, S. Cho, C. Shin, H. Yoo, S. Choi, K. Hong, S. Aritome, S. Park, and S. Hong, “Novel 3-dimensional Dual Control-gate with Surrounding Floating-gate (DC-SF) NAND flash cell for 1Tb file storage application,” in Electron Devices Meeting (IEDM), 2010 IEEE International, 2010, pp. 29.7.1–29.7.4. Available: http://dx.doi.org/10.1109/IEDM.2010.5703447
  8. M. S. Seo, B. H. Lee, S. k Park, and T. Endoh, “A Novel 3-D Vertical FG NAND Flash Memory Cell Arrays Using the Separated Sidewall Control Gate (S-SCG) for Highly Reliable MLC Operation,” in 2011 3rd IEEE International Memory Workshop (IMW), 2011, pp. 1–4. Available: http://dx.doi.org/10.1109/IMW.2011.5873208
  9. D. Kang, W. Jeong, C. Kim, D. H. Kim, Y. S. Cho, K. T. Kang, J. Ryu, K. M. Kang, S. Lee, W. Kim, H. Lee, J. Yu, N. Choi, D. S. Jang, J. D. Ihm, D. Kim, Y. S. Min, M. S. Kim, A. S. Park, J. I. Son, I. M. Kim, P. Kwak, B. K. Jung, D. S. Lee, H. Kim, H. J. Yang, D. S. Byeon, K. T. Park, K. H. Kyung, and J. H. Choi, “256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers,” in 2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, pp. 130–131. Available: http://dx.doi.org/10.1109/ISSCC.2016.7417941
  10. K. Parat and C. Dennison, “A floating gate based 3D NAND technology with CMOS under array,” in 2015 IEEE International Electron Devices Meeting (IEDM), 2015, pp. 3.3.1–3.3.4. Available: http://dx.doi.org/10.1109/IEDM.2015.7409618
  11. T. Tanaka, M. Helm, T. Vali, R. Ghodsi, K. Kawai, J. K. Park, S. Yamada, F. Pan, Y. Einaga, A. Ghalam, T. Tanzawa, J. Guo, T. Ichikawa, E. Yu, S. Tamada, T. Manabe, J. Kishimoto, Y. Oikawa, Y. Takashima, H. Kuge, M. Morooka, A. Mohammadzadeh, J. Kang, J. Tsai, E. Sirizotti, E. Lee, L. Vu, Y. Liu, H. Choi, K. Cheon, D. Song, D. Shin, J. H. Yun, M. Piccardi, K. F. Chan, Y. Luthra, D. Srinivasan, S. Deshmukh, K. Kavalipurapu, D. Nguyen, G. Gallo, S. Ramprasad, M. Luo, Q. Tang, M. Incarnati, A. Macerola, L. Pilolli, L. D. Santis, M. Rossini, V. Moschiano, G. Santin, B. Tronca, H. Lee, V. Patel, T. Pekny, A. Yip, N. Prabhu, P. Sule, T. Bemalkhedkar, K. Upadhyayula, and C. Jaramillo, “A 768Gb 3b/cell 3D-floating-gate NAND flash memory,” in 2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, pp. 142–144. Available: http://dx.doi.org/10.1109/ISSCC.2016.7417947
  12. http://toshiba.semicon-storage.com/ap-en/company/news/news-topics/2015/08/memory-20150806-1.html