3D Network-on-Chip (3D NoC) consist of switches and links and use circuit or packet switching technology to transfer data inside a 3D IC.
3D NoC architectures are generally classified into two types: symmetric and bus hybrid. However, the latter lacks concurrent communication in the vertical stack and suffers from possible contention and blocking issues in the vertical intercon- nects. The key performance metrics in 3D NoCs include zero-load latency and power consumption of the network. To optimize these two metrics, various 3D NoC topologies have been proposed.
The physical layer of a 3D NoC architecture consists of longer horizontal interconnects that connect the adjacent nodes in the same layer and shorter vertical interconnects that connect the nodes on different layers.
State of the art
In 2016 Pascal Vivet of CEA Leti and co-workers presented a homogeneous 3D circuit composed of regular tiles assembled using a 4×4×2 network-on-chip, using robust and fault tolerant asynchronous 3D links, providing 326 MFlit/s @ 0.66 pJ/b, fabricated in CMOS 65nm technology using 1980 TSVs in a face-to-back configuration
- P. Vivet, Y. Thonnart, R. Lemaire, E. Beigne, C. Bernard, F. Darve, D. Lattard, I. Miro-Panades, C. Santos, F. Clermidy, S. Cheramy, F. Petrot, E. Flamand, and J. Michailos, “A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links,” in 2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, pp. 146–147. Available: http://dx.doi.org/10.1109/ISSCC.2016.7417949