3D integration
www.3dic.org/3D integration
3D integration refers to multiplelayer integration of traditional planer microelectronic devices in the 3rd dimension.
Contents
History
Said the 1965 Nobel Physics laureate, Richard Feynman at the Gakushuin University (Tokyo) in 1985: “Another direction of improvement (of computing power) is to make physical machines three dimensional instead of all on a surface of a chip (2D). That can be done in stages instead of all at once – you can have several layers and then add many more layers as time goes on.”
3D Schemes
3D packaging
3D packaging refers to 3D integration schemes that rely on traditional methods of interconnect such as wire bonding and FlipChip to achieve vertical chip or package (PackageonPackage or PoP) stacks.
2.5D Integration
2.5D integration refers to the technology that stacks active chips sidebyside on a passive Si/glass interposer (or the intel's embedded multidie interconnect bridge, EMIB), which enables high density chiptochip interconnects.
Parallel 3D integration
Parallel 3D integration, also called stacked 3D integration, refers to a 3D integration scheme, in which devices on separate wafers are fabricated in parallel prior to 3D stacking and vertically interconnecting.
Sequential 3D integration
Sequential 3D integration, also called monolithic 3D integration, refers to fabricating devices on different stacked/transferred layers sequentially on the same wafer. The stacked layers can be made of Si CMOS, highmobility semiconductors such as Ge for pMOS and GaAs or InP for nMOS, and transition metal dichalcogenide (TMD) for nMOS or pMOS. Widebandgap semiconductors can also be integrated for some applications.
Technologies
3D Applications/ Demonstrations 

2.5D/3D Schemes  
Bonding Schemes  
Bonding Methods 

3D Interconnects 

Electrical Design  
Thermal,
ThermalMechanical, LowPower Design 

Related Articles
References