3D integration refers to multiple-layer integration of traditional planer microelectronic devices in the 3rd dimension.
Said the 1965 Nobel Physics laureate, Richard Feynman at the Gakushuin University (Tokyo) in 1985: “Another direction of improvement (of computing power) is to make physical machines three dimensional instead of all on a surface of a chip (2D). That can be done in stages instead of all at once – you can have several layers and then add many more layers as time goes on.”
3D packaging refers to 3D integration schemes that rely on traditional methods of interconnect such as wire bonding and Flip-Chip to achieve vertical chip or package (Package-on-Package or PoP) stacks.
2.5D integration refers to the technology that stacks active chips side-by-side on a passive Si/glass interposer (or the intel's embedded multi-die interconnect bridge, EMIB), which enables high density chip-to-chip interconnects.
Parallel 3D integration
Parallel 3D integration, also called stacked 3D integration, refers to a 3D integration scheme, in which devices on separate wafers are fabricated in parallel prior to 3D stacking and vertically interconnecting.
Sequential 3D integration
Sequential 3D integration, also called monolithic 3D integration, refers to fabricating devices on different stacked/transferred layers sequentially on the same wafer. The stacked layers can be made of Si CMOS, high-mobility semiconductors such as Ge for p-MOS and GaAs or InP for n-MOS, and transition metal dichalcogenide (TMD) for n-MOS or p-MOS. Wide-bandgap semiconductors can also be integrated for some applications.
|3D Applications/ Demonstrations||
Thermal-Mechanical, Low-Power Design