3D memory

www.3dic.org/3D memory

3D memory refers to a memory having vertically stacked device layers or dies for improved bandwidth (like HBM and HCM), latency, and capacity (like NAND flash and SSDs). 3D memory can be realized by making vertical channels/gates or by 3D stacking of memories with horizontal channels and horizontal gates. 3D stacking also enables stacking of volatile memory like DRAM directly on top of a processor, significantly reducing transmission delay and power dissipation between the two blocks.

Key Players

Type Companies
3D NAND (vertical channel, gate-all-around) Samsung, Toshiba, SK Hynix, Intel/Micron, SanDisk
3D NAND (vertical gate) Macronix
3D NAND with TSVs Toshiba
Wide IO (with TSVs) Samsung, SK Hynix
HBM (with TSVs) AMD, SK Hynix
HMC (with TSVs) Micron
3D stacked memory with wire bonding Elpida
3D SRAM (S3 SRAM) Samsung

3D Memory Using Stacked Polysilicon

3D Memory Using Stacked Crystal Silicon

3D Memory Using TSVs

Patents Related to 3D Memory Using TSVs

Patent NO. Assignee Patent Title Filling Date
US20140192606A1 Samsung Stacked memory device, memory system including the same and method for operating the same Dec. 11, 2013
US20130037944 A1 Samsung Chip Stack Packages Having Aligned Through Silicon Vias of Different Areas 2012年8月7日

3D Memory Using Wire Bonding

Elpida 3D stacked using in A7

3D Memory Stacked on Processor

The memory and processor always co-exist in a computing device. The processor has controller that communicates with the memory. The memory and processors are usually designed in different manufacturing process technology nodes due to cost and performance advantages.


  • B. Prince, Ed., Vertical 3D Memory Technologies. Chichester, United Kingdom: John Wiley & Sons Ltd, 2014. Online ISBN: 9781118760475.
  • R. Micheloni, Ed., 3D Flash Memories. Dordrecht: Springer Netherlands, 2016.


Knowmade, TSV Stacked Memory Patent Landscape, http://www.knowmade.com/downloads/tsv-stacked-memory-patent-landscape/