3D stacked image sensor

www.3dic.org/3D stacked image sensor

A 3D stacked image sensor consists of a backside-illuminated image sensor die face-to-face stacked on a logic die.

History

Announcement Date Stacked layers Stacking technology Company/Product model Product
2016 [1] TMD phototransistor on logic/memory Sequential 3D integration National Nano Device Laboratories and National Tsinghua University, Taiwan
2016 [2] Microbump (7.6-µm pitch) Olympus Corporation
2016 [3] CIS + ISP Hybrid bonding (DBI) Sony IMX260 Samsung Galaxy S7
2016 [4] CIS + ISP The University of Edinburgh, STMicroelectronics non-mass production
2016 [5] CIS + ISP Hybrid bonding STMicroelectronics, CEA Leti non-mass production
2016 [6] CIS + ISP TSMC non-mass production
2016[7] CIS + ISP (row drivers/decoders, load transistors, analog MUX, column readouts, a shift register, and other peripheral circuits, where the individual column readouts consist of a

PGA and an 11b SS-ADC)

Toshiba non-mass production
2015[8] CIS + ISP Au/SiO2 hybrid bonding NHK and Univ. of Tokyo non-mass production
2015 Olympus
2015 On Semiconductor
2014 CIS + ISP F2F bonding + W-TSVs Samsung S5K3P3SX
2012 CIS + ISP Oxide bonding (ZiBond) + via-last TSVs Sony

Parallel 3D integration

Sony IMX260 DBI.jpg
Sony's IMX260 3D stacked image sensor made by DBI bonding technology.

Sequential 3D integration

Researchers at National Nano Device Laboratories and National Tsinghua University, Taiwan, demonstrated a monolithic 3D image sensor by sequentially fabricating monolayer (<1nm) TMD phototransistor array by using CVD-grown MoS2 transferred onto top of a 3D logic/memory hybrid 3D IC connected by high density interconnect.[1]

3D image sensor with TMD phototransistor.png
(a) Schematic illustration of a monolithic 3D image sensor including (b) the top monolayer TMD phototransistor array and (c) the bottom low thermal budget 3D IC connected by high density interconnect.[1]


References

  1. 1.0 1.1 1.2 C. C. Yang, K. C. Chiu, C. T. Chou, C. N. Liao, M. H. Chuang, T. Y. Hsieh, W. H. Huang, C. H. Shen, J. M. Shieh, W. K. Yeh, Y. H. Chen, M. C. Wu, and Y. H. Lee, “Enabling monolithic 3D image sensor using large-area monolayer transition metal dichalcogenide and logic/memory hybrid 3D+IC,” in 2016 IEEE Symposium on VLSI Technology, 2016, pp. 1–2. Available: http://dx.doi.org/10.1109/VLSIT.2016.7573448
  2. T. Kondo, N. Takazawa, Y. Takemoto, M. Tsukimura, H. Saito, H. Kato, J. Aoki, K. Kobayashi, S. Suzuki, Y. Gomi, S. Matsuda, and Y. Tadaki, “3-D-Stacked 16-Mpixel Global Shutter CMOS Image Sensor Using Reliable In-Pixel Four Million Microbump Interconnections With 7.6- Pitch,” IEEE Transactions on Electron Devices, vol. 63, no. 1, pp. 128–137, Jan. 2016. Available: http://dx.doi.org/10.1109/TED.2015.2442611
  3. Y. Kagawa et al. Novel Stacked CMOS Image Sensor with Advanced Cu2Cu Hybrid Bonding, IEDM, 2016.
  4. T. Al Abbas et al. Backside Illuminated SPAD Image Sensor with 7.83μm Pitch in 3D-Stacked CMOS Technology, IEDM, 2016.
  5. S. Lhostis, A. Farcy, E. Deloffre, F. Lorut, S. Mermoz, Y. Henrion, L. Berthier, F. Bailly, D. Scevola, F. Guyader, F. Gigon, C. Besset, S. Pellissier, L. Gay, N. Hotellier, M. Arnoux, A.-L. Le Berrigo, S. Moreau, V. Balan, F. Fournel, A. Jouve, S. Chéramy, B. Rebhan, G. A. Maier, and L. Chitu, Reliable 300 mm Wafer Level Hybrid Bonding for 3D Stacked CMOS Image Sensors, in 2016 IEEE 66th Electronic Components and Technology Conference, Las Vegas, NV, USA, 2016, pp. 869–876.
  6. C. C. M. Liu, M. M. Mhala, C. H. Chang, H. Tu, P. S. Chou, C. Chao, and F. L. Hsueh, A 1.5V 33Mpixel 3D-stacked CMOS image sensor with negative substrate bias, in 2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, pp. 124–125. Available: http://dx.doi.org/10.1109/ISSCC.2016.7417938
  7. K. Shiraishi, Y. Shinozuka, T. Yamashita, K. Sugiura, N. Watanabe, R. Okamoto, T. Ashitani, M. Furuta, and T. Itakura, “A 1.2e- temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA,” in 2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, pp. 122–123. Available: http://dx.doi.org/10.1109/ISSCC.2016.7417937
  8. M. Goto, K. Hagiwara, Y. Iguchi, H. Ohtake, T. Saraya, M. Kobayashi, E. Higurashi, H. Toshiyoshi, and T. Hiramoto, “Pixel-Parallel 3-D Integrated CMOS Image Sensors With Pulse Frequency Modulation A/D Converters Developed by Direct Bonding of SOI Layers,” IEEE Transactions on Electron Devices, vol. 62, no. 11, pp. 3530–3535, Nov. 2015. Available: http://dx.doi.org/10.1109/TED.2015.2425393