Chip-on-Wafer-on-Substrate (CoWoS®)

www.3dic.org/CoWoS

TSMC CoWoS® (Chip-on-Wafer-on-Substrate) technology integrates multiple chips side-by-side onto a interposer containing through-silicon vias (TSVs) by chip-to-wafer bonding process, which is followed by CoW chip assembly onto a substrate (CoW-on-Substrate).

Applications

  • In June 2011, Xilinx demonstrated 2.5D FPGA based on the CoWoS process [1][2]. The 2.5D FPGA chip is a 4-slice 28nm chip side-by-side mounted on a 25 x 31 mm 100um thick interposer with thousands of microbumps at 45um pitch. The TSV interposer is assembled on a 42.5 x 42.5 mm organic package with 180um pitch C4 bumps.
  • March 22, 2012 – Altera Corporation and TSMC announced the joint development of the heterogeneous 3D IC test vehicle using TSMC's CoWoS integration process.
  • Oct. 12, 2012 – TSMC announced that it has taped out the foundry segment's first CoWoS test vehicle using JEDEC Solid State Technology Association's Wide I/O mobile DRAM interface. Partners include: Wide I/O DRAM from SK Hynix; Wide I/O mobile DRAM IP from Cadence Design Systems; and EDA tools from Cadence and Mentor Graphics. The milestone demonstrates the industry's system integration trend to achieve increased bandwidth, higher performance and superior energy efficiency.
  • Oct. 21, 2013 – Xilinx Inc. and TSMC announced production release of the Virtex-7 HT family developed on TSMC's CoWoS process. With this milestone, all Xilinx 28nm 3D IC families are now in volume production.
  • In April 2016, Nvidia announced its Tesla P100 GPU with HBM2 based on TSMC's CoWoS process.

References

  1. B. Banijamali, S. Ramalingam, K. Nagarajan, and R. Chaware, “Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA,” in Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st, 2011, pp. 285–290. Available: http://dx.doi.org/10.1109/ECTC.2011.5898527
  2. R. Chaware, K. Nagarajan, and S. Ramalingam, “Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer,” in Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd, 2012, pp. 279–283. Available: http://dx.doi.org/10.1109/ECTC.2012.6248841