Direct bonding is a wafer bonding technology which obtains bonding between surfaces without using intermediate layers, such as solder and adhesives.
Dielectric bonding using inorganic dielectrics has been extensively investigated for mi-cro-electro-mechanical systems (MEMS), III-V/Si photonic integration, and heterogeneous integration in the last 30 years. The various bonding techniques are based on a similar hydrophilic bonding mechanism, i.e., the bonding is achieved through polymerization of surface OH groups into covalent bonds across the bonding interface. Bonding using SiO2 films is most widely studied among many other inorganic dielectrics, mainly because SiO2 is readily formed on a Si wafer sur-face (native oxide or wet chemical oxide) or can be formed easily through thermal oxidation or deposition. Dielectric bonding has been widely used for Sequential 3D integration and fabrication of Semiconductor-on-Insulator advanced substrates such as Si-on-insulator (SOI), Si-on-diamond (SOD), Ge-on-insulator (GOI), and III-V-on-insulator (III-V-OI) such as InP-on-insulator, InGaAs-on-insulator (InGaAsOI), and GaAs-on-insulator (GaAsOI), etc.
The pioneering works of hydrophilic bonding were published in 1986, when J. B. Lasky of IBM demonstrated hydrophilic Si wafer bonding with a 500 nm thermally grown SiO2 layer on ei-ther or both silicon wafers (i.e., Si–SiO2 and SiO2–SiO2 bonding), while M. Shimbo et al. of Toshiba reported Si wafer bonding with thin native oxide on both surfaces (i.e., Si–Si bonding). The first detailed study of hydrophilic wafer bonding was published in 1988 by W. P. Maszara et al. They introduced the double cantilever beam technique for bonding strength measurements (in terms of surface energy γ or bonding energy G = 2γ) based on Gillis and Gilman’s work. This bonding strength measurement method is also known as the “crack opening” or “blade insertion” method and it has been widely used because of its simplicity to perform. In 1989, R. Stengl et al. presented the first multi-stage model for hydrophilic wafer bonding. In 1996, Q.-Y. Tong et al. further devel-oped the multi-stage model based on their 1994 study of bonding energy evolution of room temperature (RT) bonded hydrophilic wafers during storage at various temperatures. According to the model, besides the basic requirements of surface flatness, smoothness, and clean-ness, a highly hydrophilic wafer surface terminated with ≡Si–OH (silanol) is desired for bonding formation. At the initial stage, wafers are bonded via hydrogen bonds between wafers with trapped H2O molecules. During postbonding annealing at elevated temperatures, the polymerization of each ≡Si–OH pair results in one covalent ≡Si–O–Si≡ (siloxane) bond at the bonding interface:
The above reaction indicates the bonding strength is related to the numbers of ≡Si–OH pairs be-tween the mating wafers at temperatures below oxide melting temperature (as >800°C). To increase the the number of ≡Si–OH, various surface cleaning and treatments have been developed for prebonding surface activation. Among many other treatment methods, plasma activation by using reactive ion etching (RIE) plasma, also called plasma-activated wafer bonding (PAWB), has been extensively studied since S. N. Farrens et al. reported a detailed research of Si–Si, Si–SiO2 and SiO2–SiO2 bonding, in 1995. Nowadays, the postbonding annealing temperature in PAWB is typically in range of 200-400 °C for Si–SiO2 bonding and 300-400 °C for Si–Si and SiO2–SiO2 bonding, respectively. The hydrophilic bonding can also be applied for various inor-ganic materials, such as Al2O3 and SiNx, based on the similar mechanism.
Bonding of metal (Pd spheres) was first demonstrated by J. T. Desaguliers in 18th century. In microelectronics industry, wire bonding technologies, such as thermocompression bonding and thermosonic bonding, was developed in 1950s–1970s. The famous flip-chip packaging technology with controlled collapse chip connection (C4) solder bumps was developed by IBM in 1960s. To improve the reliability of a flip-chip package, Hitachi introduced the underfilling technology to fill the gaps between the chip and substrate, in 1987. The flip-chip technology has been widely used to replace the wire bonding technology for finer interconnect pitch. In 2000s, Pd-free solders, such as Sn-Ag-Cu, were developed to meet the requirement of the Restriction of Hazardous Substances Directive (RoHS). Since then, metal bonding using other metal materials has also been widely in-vestigated by academia and industry.
Soldering is based on reflow of solders at tem-peratures higher then their melting points. For the widely used Sn-3.0Ag-0.5Cu, the melting points are 217 °C/220 °C (solidus/liquidus temperatures), and the peak temperature of the reflow profile is typically around 245 °C. The soldering forms intermetallic compounds (IMCs) and results in an IMCs/solder/IMCs interface structure. As the pitch gets finer, reflow of solder bumps may cause electrical short due to bridging. In order to avoid bridging between solder bumps, Cu pillar with a low-melting-point metal cap (e.g., Sn and Sn-Ag) was developed. By con-trolling the thickness of the low-melting-point metal cap, bonding can be achieved through sol-id-liquid (solid-liquid interdiffusion (SLID) bonding) or solid-state (solid-state interdiffusion (SSID) bonding) reactions between Cu and low-melting-point metals, consuming all the low-melting-point metals and forming IMCs at the bonding interface. Comparing to the sol-dering and SLID bonding, the SSID bonding is performed at lower temperatures (below the melting points, e.g., 232 °C of Sn) but under higher bonding pressures (~50-150 MPa).
Metal bonding based on formation of IMCs limits the electrical conductivity, reliability (since cracks are prone to occur at solder-IMCs interface or inside IMCs), and the minimum pitch of con-nects. Direct Cu–Cu bonding without use of solders or formation of IMCs at the bonding interface, has been developed to solve these concerns. Comparing to other direct metal bonding such as Al–Al bonding, Cu–Cu bonding promises better electrical conductivity, power consumption, resistive-capacitive (RC) delay, and electromigration resistance. In addition, Cu interconnects also provide excellent heat dissipation and thermal reliability, which meets the requirements of some applications such as power electronics with an operation temperature as high as 250 °C. Therefore, Cu–Cu bonding is a great candidate to achieve electrical and thermal in-terconnections with high electrical performance, interconnects density, and thermal/mechanical re-liability for 3D stacked devices.
The study of Cu–Cu bonding started at universities around 2000, soon after the announcement of Cu interconnects for integrated circuits by IBM in 1997. In Cu–Cu bonding, the Cu films can be depostied on a wafer by using sputtering deposition, electron beam evaporation, and electro/electroless plating. A main challenge of Cu–Cu bonding is that Cu surface is readily oxidized during exposure to air by O2 and H2O, and the resulted thick (>10 nm) Cu oxides (CuO and Cu2O) prevent bonding formation at below 300 °C. Two main bonding methods have been developed for Cu–Cu bonding, i.e., thermal compression bonding (TCB) and surface activated bonding (SAB).
Semiconductor Bonding (without oxide interlayers)
Semiconductor bonding wihtout oxide interlayers has been realiazed by the hydrophobic bonding method and the surface activated bonding (SAB) method.