Embedded Multi-die Interconnect Bridge (EMIB) is an approach developed by Intel to in-package high density interconnect of heterogeneous chips. The industry refers to this application as 2.5D package integration. Instead of using a large Si interposer typically found in other 2.5D approaches (like TSMC's CoWoS and Unimicron's embedded interposer carrier), EMIB uses a very small bridge die with multiple routing layers, but without TSVs. This bridge die is embedded as part of Intel's substrate fabrication process.


EMIB was first proposed in the mid-2000s by Mahajan and Sane [1]. It was further extended by the work of Braunisch et.al [2] and Starkston et.al [3] to evolve to its current instantiation.

Altera is enabling next-generation platforms with 3D SiP technology built with Intel’s EMIB. [4] Altera has launched the Stratix 10 FPGA which consists of HBM2 3D DRAM combined with FPGAs by using the EMIB.

Heterogeneous Integration using EMIB

The basic concept of EMIB is that it uses thin pieces (below 75um) of silicon with multi-layer and fine-pitch BEOL interconnects (2um lines & 2um spaces ), embedded in an organic substrate, to enable localized dense die-to-die interconnects between dies assembled on the substreate. Figure 1 shows a schematic diagram of heterogeneous integration using EMIB.

Heterogeneous Integration using EMIB.png
Figure 1. Heterogeneous Integration using EMIB.

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Figure 2. Schematic showing the EMIB architecture. (a) Cross-section view; (b) top view of a test vehicle and its design layout to highlight localized high density interconnects and pitches.[5]

EMIB vs. Interposer

EMIB vs Interposer.png
EMIB versus Interposer for 2.5D integration (CoWoS).


  1. US patent no. 8,064,224, “Microelectronic package containing silicon patches for high density interconnects , and method of manufacturing same,” Inventors: Ravi Mahajan and Sandeep Sane.
  2. H. Braunisch, A. Aleksov, S. Lotz, and J. Swan, “High-speed performance of silicon bridge die-to-die interconnects,” in Proc. IEEE Conf. Electrical Perf. Electronic Packaging and Systems (EPEPS), San Jose, CA, Oct. 23–26, 2011, pp. 95–98.
  3. US patent no. 9,136,236, “Localized High Density Substrate Routing,” Inventors: Robert Starkston, Debendra Mallik, John Guzek, Chia-Pin Chiu, Deepak Kulkarni, and Ravi Mahajan.
  4. https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/wp/wp-01251-enabling-nextgen-with-3d-system-in-package.pdf
  5. R. Mahajan, R. Sankman, N. Patel, D. W. Kim, K. Aygun, Z. Qian, Y. Mekonnen, I. Salama, S. Sharan, D. Iyengar, and D. Mallik, “Embedded Multi-die Interconnect Bridge (EMIB) – A High Density, High Bandwidth Packaging Interconnect,” in 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2016, pp. 557–565. Available: http://dx.doi.org/10.1109/ECTC.2016.201