Fan-Out Wafer-Level Packaging (FOWLP)

www.3dic.org/FOWLP

Fan-out wafer-level packaging (FOWLP) is a is an enhancement of standard wafer-level packaging (WLP, also known as WLCSP) for a greater number of external I/Os and system-in-package (SiP) solutions. FOWLP involves dicing chips on a silicon wafer, and then very precisely positioning the known-good chips on a thin “reconstituted” or carrier wafer/panel, which is then molded, following by making redistribution layer atop the molded area (chip and fan-out area), and then forming solder balls on top.

History

  • FOWLP made its first appearance with the introduction of embedded wafer level ball grid array (eWLB) from Infineon. The eWLB was introduced by Infineon in fall 2007 and then jointly developed by Infineon, and STMicroelectronics, STATS ChipPAC, through a formerly-declared coalition with its technology associates in 2008. In early 2009, Infineon was the first company to commercialize its own eWLB packaging technology in an LG cell-phone. The same eWLB product is in production in some Nokia handsets since 2010.
  • In 2013, C. Scanlan at Deca Technologies, Inc. proposed a fully molded FOWLP approach.[1]
    Cross-section of a fabricated fully molded FOWLP. (Deca Technologies, Inc.)
  • In 2014, the High Density Fan-out Wafer Level Packaging (FOWLP) Consortium led by A*Star IME was launched.[2] The members include Amkor, Nanium, STATS, NXP, GlobalFoundries, K&S, Applied Materials, Dipsol, JSR, KLA-Tencor, Kingyoup, Orbotech and TOK.
  • In 2016, the Multi-chip Fan-out Wafer Level Packaging Development Line Consortium (FOWLP DLC) led by A*Star IME was launched.[3]
  • In 2016, TSMC used its integrated fan-out (InFO) packaging for Apple's A10 processors for use in the iPhone 7 series.
  • In Oct. 2016, Advanced Semiconductor Engineering (ASE) has reportedly obtained orders for FOWLP from Qualcomm, MediaTek and HiSilicon with volume production set to kick off by the end of 2016, according to DIGITIMES[4].

Advantages

"Fan-out is perhaps the biggest thing to hit the semiconductor industry since immersion lithography and high-k dielectrics."[5]

Fan-out Wafer Level Packages like eWLB offer the following differentiated advantages:

  • Over Flip-Chip Packaging:
    • Slightly smaller footprint (clearance distances to the edges are smaller)
    • Thinner package
    • Substrate-less package (shorter interconnections meaning higher electrical performance and cheaper in the long run)
    • Future potential for SiP and 3D integration
    • Lower thermal resistance
    • Simplified supply chain infrastructure
  • Over Fan-In WLCSP:
    • Higher board-level reliability
    • Fan-out area to counter the pad limitation issue, adaptable to customer needs
    • Only confirmed known good dice are packaged
    • Potential for SiP integration
    • Lower thermal resistance
    • Built-in back-side protection
    • No restriction in bump pitch
FI and FO.png
Comparison between (a) fan-in WLP (CSP), (b) flip-chip package, (c) encapsulated fin-in, and (d) fan-out WLP.

Wafer-level and Panel-level FOWLP

The industry is working on fan-out based on a panel or square format for cost reduction. The panel format enables more die, thereby lowering costs. For example, a 300mm wafer enables 616 packages at 10x10-mm2, while an 18x24inch2 panel produces 1911 packages.

Chip-first (mold-first) and Chip-last (RDL-first) FOWLP

Chip-first is a process whereby the die is attached to a temporary or permanent material structure prior to making the RDL that will extend from the die to BGA interface. In this manner, the yield loss associated with creating the RDL occurs after the die is mounted, subjecting the die to potential loss.

In chip-last prosess, RDL is created first and then the die is mounted. In this flow, the RDL structures can either be electrically tested or visually inspected for yield loss, thereby avoiding placing good die on bad sites.

For low I/O die, where RDL is minimal and yields are very high (>99%), a chip-first flow is preferred. However, for high value die (large I/O), a chip-last process is preferred.

Mold-first and RDL-first FOWLP.png

3D FO

sys-plus-3.jpg

FO-MCM, FO-PoP, and FO-SiP

FOWLP Suppliers

Company Technology Wafer/Panel Level Products
Infineon eWLB since 2009
STATS ChipPAC eWLB (license from Infineon)
ASE eWLB (license from Infineon) Panel/Wafer
NANIUM eWLB (license from Infineon)
TSMC InFO Apple A10
Amkor SWIFT™ (Silicon Wafer Integrated Fan-out Technology) and
SLIM™ (Silicon-less integrated module)
Deca Technologies M-Series™
ADL Engineering pWLB (Panel Wafer Level BGA) Panel
Fujikura WABE PackageTM (wafer and board level device embedded package)
NEPES
Freescale Redistributed Chip Packaging (RCP)
Powertech Technology Inc. (PTI) Panel
SPIL (矽品)
Kunshan Huatian Technology Electronics Embedded Si Fan-Out (eSiFO) Wafer