High Bandwidth Memory (HBM)

www.3dic.org/HBM

High Bandwidth Memory (HBM) is a TSVs-based 3D DRAM from AMD and SK Hynix. High volume manufacturing began at a SK Hynix facility in Icheon, Korea, in 2015. The first product to use HBM is the AMD Radeon R9 Fury X GPU released in June 2015. The HBM stacks and GPU are assembled on a Si interposer side-by-side through the 2.5D integration. The first product utilizing HBM2 is the Nvidia Tesla P100 GPU which was officially announced in April 2016.

Standards

  • HBM has been adopted as industry standard JESD235 by JEDEC in October 2013;
  • HBM2 was accepted by JEDEC as standard JESD235A in Nov. 2015.[1]


Products

Announcement Date Company Product HBM 1&2 Memory Bandwidth Packaging Technology
June 2015 AMD Radeon R9 Fury X GPU (Fiji) HBM1 × 4 (1024×4 bit) 512 Gbps CoWoS
June 2015 Altera Stratix 10 FPGA HBM2 × 4 EMIB
April 2016 Nvidia Tesla P100 GPU HBM2 × 4 CoWoS

Multi-Die Technology for HBM

  1. MCM: Multi-chip Module
  2. FO-MCM: Fan-out MCM
  3. FL-MCM: Fine-line MCM
  4. CoWoS: Chip-on-Wafer-on-Substrate
  5. NTI: No TSV Interconnection
  6. SLIM: Silicon-Less Integrated Module
  7. EMIB: Embedded Multi-die Interconnect Bridge

Amd sk hynix hbm.jpg
AMD GPU/SK Hynix HBM stack with TSVs and microbumps attached on a Si interposer on a package substrate.

SK Hynix HBM 2015.png
SK Hynix HBM stack with TSVs and microbumps attached on a Si interposer on a package substrate.

References

  1. JESD235A, HIGH BANDWIDTH MEMORY (HBM) DRAM, http://www.jedec.org/standards-documents/results/JESD235