Pitch: C4 bump reflow < solder microbump reflow < Cu pillar with solder capping thermal-compression bonding < Cu microbump and Cu-Cu bonding
|2.5 μm||4 μm||Bumpless Cu/SiO2 Hybrid bonding (DBI)||2013, Fermi Lab |
|2.5 μm||5 μm||Au cone bumps||2015, Tohoku-MicroTec Co., Ltd. |
|3 μm||6 μm||Bumpless Cu-Cu bonding (SAB)||2008, Univ. of Tokyo |
|3 μm||6 μm||Bumpless Cu-Cu bonding (thermal compression bonding)||2012, Nanyang Technological Univeristy |
|–||7.6 µm||Microbumps||2016, Olympus Corporation |
Au and Cu Cone Bumps
see Cone bumps
Reseachers at Kyushu Institute of Technology proposed the compliant bumps such as pyramid bumps and cone bumps. In 2005, they demonstrated bonding with Au cone bumps with bump size/pitch of 10 µm/20 µm .
In 2011, N. Watanabe and T. Asano reported Cu-Cu bonding at room temperature using Cu cone bumps and Cu landing with cross-shaped slit .
Reflow vs. Thermal-compression bonding
- In June 2011, Xilinx demonstrated 2.5D FPGA based on the CoWoS process, using thousands of microbumps at 45µm pitch for chip-to-wafer bonding .
- In 2016, researchers at Olympus Corporation demonstrated a 3D-stacked 16-Mpixel CIS with four million interconnections in a 7.6-µm pitch that connects every four pixels on the top substrate to the corresponding storage node on the bottom substrate to achieve both a 16-Mpixel GS mode with a PLS of −180 dB and 2-Mpixel high-speed image-capturing mode .
- R. Yarema, G. Deptuch, and R. Lipton, “Recent results for 3D pixel integrated circuits using copper-copper and oxide-oxide bonding,” PoS (VERTEX 2013), vol. 32, 2013.
- M. Motoyoshi, T. Miyoshi, M. Ikebec, and Y. Arai, “3D integration technology for sensor application using less than 5μm-pitch gold cone-bump connpdfection,” Journal of Instrumentation, vol. 10, no. 3, pp. C03004–C03004, Mar. 2015. Available: http://dx.doi.org/10.1088/1748-0221/10/03/C03004
- A. Shigetou, T. Itoh, K. Sawada, and T. Suga, “Bumpless Interconnect of 6-μm-Pitch Cu Electrodes at Room Temperature,” IEEE Transactions on Advanced Packaging, vol. 31, no. 3, pp. 473–478, Aug. 2008. Available: http://dx.doi.org/10.1109/TADVP.2008.920644
- L. Peng, L. Zhang, J. Fan, H. Y. Li, D. F. Lim, and C. S. Tan, “Ultrafine Pitch (6 μm) of Recessed and Bonded Cu-Cu Interconnects by Three-Dimensional Wafer Stacking,” IEEE Electron Device Letters, vol. 33, no. 12, pp. 1747–1749, Dec. 2012. Available: http://dx.doi.org/10.1109/LED.2012.2218273
- T. Kondo, N. Takazawa, Y. Takemoto, M. Tsukimura, H. Saito, H. Kato, J. Aoki, K. Kobayashi, S. Suzuki, Y. Gomi, S. Matsuda, and Y. Tadaki, “3-D-Stacked 16-Mpixel Global Shutter CMOS Image Sensor Using Reliable In-Pixel Four Million Microbump Interconnections With 7.6- Pitch,” IEEE Transactions on Electron Devices, vol. 63, no. 1, pp. 128–137, Jan. 2016. Available: http://dx.doi.org/10.1109/TED.2015.2442611
- N. Watanabe, T. Kojima, and T. Asano, “Wafer-level compliant bump for three-dimensional LSI with high-density area bump connections,” in IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 2005, pp. 671–674. Available: http://dx.doi.org/10.1109/IEDM.2005.1609440
- N. Watanabe and T. Asano, “Room-Temperature Cu–Cu Bonding in Ambient Air Achieved by Using Cone Bump,” Appl. Phys. Express, vol. 4, no. 1, p. 16501, Jan. 2011. Available: http://dx.doi.org/10.1143/APEX.4.016501
- B. Banijamali, S. Ramalingam, K. Nagarajan, and R. Chaware, “Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA,” in Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st, 2011, pp. 285–290. Available: http://dx.doi.org/10.1109/ECTC.2011.5898527