Multichip-to-wafer bonding

www.3dic.org/Multichip-to-wafer bonding


State-of-the-art

  • Researchers at Tohoku University developed a multichip-to-wafer bonding method using surface tension-powered multichip self-assembly [1]. Many chips are self-assembled to a carrier wafer named “reconfigured wafer”, before the reconfigured wafer-to-wafer bonding.
Multichip self-assembly process.png
Multichip self-assembly process for mutipchip-to-wafer bonding. (T. Fukushima et al. 2011)


  • IME has developed a 20μm pitch micro-bump array assembly process with throughput of 1200 UPH (or 3 sec/chip) and bonding accuracy <2um by using two-step C2W bonding. The C2W is carried out in two steps where in the first step chips are temporary tacked on the wafer with wafer-level underfill planarized by diamond bit cutting, and in the second step, fully populated tacked chips on wafer are permanently bonded by using pressurized gas in a gas-pressure gang bond process.[2]


References

  1. T. Fukushima, E. Iwata, Y. Ohara, M. Murugesan, J. Bea, K. Lee, T. Tanaka, and M. Koyanagi, “Multichip Self-Assembly Technology for Advanced Die-to-Wafer 3-D Integration to Precisely Align Known Good Dies in Batch Processing,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 1, no. 12, pp. 1873–1884, Dec. 2011. Available: http://dx.doi.org/10.1109/TCPMT.2011.2160266
  2. L. Xie, S. Wickramanayaka, B. Y. Jung, J. A. J. Li, L. Jung-kai, and D. Ismael, “Wafer level underfill study for high density ultra-fine pitch Cu-Cu bonding for 3D IC stacking,” in Electronics Packaging Technology Conference (EPTC), 2014 IEEE 16th, 2014, pp. 400–404. Available: http://dx.doi.org/10.1109/EPTC.2014.7028388