Parallel 3D integration 3D integration

Parallel 3D integration, also called stacked 3D integration, refers to a 3D integration scheme, in which devices on separate wafers are fabricated in parallel prior to 3D stacking and vertically interconnecting.


Table I. List of reported Parallel 3D integration.
Organization (Technology) Stacked layers Bump-less or Bump-based Bonding
MIT SOI Bump-less Oxide bonding with post-bonding TOVs
IBM Bump-less Oxide bonding
WOW Alliance, Japan Bump-less Adhesive bonding with post-bonding TSVs
Univ. of Tokyo, Japan Bump-less Cu-Cu bonding (SAB)
Sony, Japan Two-layer, CIS on logic Bump-less DBI
NHK, Japan[1] Two-layer, n-MOS on p-MOS Bump-less Au/SiO2 hybrid bonding
Georgia Tech, USA (3D-MAPS) Bump-base Microbumps
University of Michigan, USA (Centip3De) Two-layer, DRAM on processor Bump-base Microbumps
(Wide IO) Bump-base Microbumps
AMD and SK Hynix (HBM) Bump-base Microbumps
Hybrid Memory Cube Consortium (HMC) TSVs-based 3D DRAM Bump-base Microbumps

Bumpless Parallel 3D Integration

TSV-last after bonding

  • Parallel 3D Integration Using Direct Oxide Bonding
Parallel 3D Integration using SOI wafers was developed by MIT [2] and IBM [3], by using oxide-oxide direct bonding (SiO2–SiO2 bonding).

The stacked layers are connected by post-bonding through-oxide vias (TOVs, or called 3D vias).

  • Wafer-on-Wafer (WOW) Using Adhesive Wafer Bonding

The WOW Alliance, Japan developed a WOW 3D integration approach by using wafer bonding (adhesive bonding), wafer thinning, and TSVs technologies. [4]

WOW stack.png
Cross-sectional SEM pictures of a) WOW stack and b) ultra-thin DRAM wafer, respectively.[4]

TSV-first, TSV-middle, TSV-last before bonding

  • Parallel 3D Integration Using Hybrid Bonding

Bump-based Parallel 3D Integration

Related News


  1. M. Goto, K. Hagiwara, Y. Iguchi, H. Ohtake, T. Saraya, E. Higurashi, H. Toshiyoshi, and T. Hiramoto, “3-D Silicon-on-Insulator Integrated Circuits With NFET and PFET on Separate Layers Using Au/SiO2 Hybrid Bonding,” IEEE Transactions on Electron Devices, vol. 61, no. 8, pp. 2886–2892, Aug. 2014. Available:
  2. V. Suntharalingam, R. Berger, S. Clark, J. Knecht, A. Messier, K. Newcomb, D. Rathman, R. Slattery, A. Soares, C. Stevenson, K. Warner, D. Young, L. P. Ang, B. Mansoorian, and D. Shaver, “A 4-side tileable back illuminated 3D-integrated Mpixel CMOS image sensor,” in Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International, 2009, pp. 38–39,39a. Available:
  3. S. J. Koester, A. M. Young, R. R. Yu, S. Purushothaman, K.-N. Chen, D. C. La Tulipe, N. Rana, L. Shi, M. R. Wordeman, and E. J. Sprogis, “Wafer-level 3D integration technology,” IBM J. Res. Dev., vol. 52, no. 6, pp. 583–597, Nov. 2008. Available:
  4. 4.0 4.1 T. Ohba, “Production-worthy WOW 3D integration technology using bumpless interconnects and ultra-thinning processes,” in 2016 IEEE Symposium on VLSI Technology, 2016, pp. 1–2. Available: