Raised source/drain

www.3dic.org/Raised source/drain

Raised source/drain refers to the source and drain regions formed above the channel to realize shallow junctions required to minimize short channel effects (series resistance) [1]. Selective Si or SiGe epitaxy is used for the epitaxial growth.

In the CoolCube, a sequential 3D integration technology developed by Leti, the SiGe27% Raised source/drain epitaxy temperature was lowered to 650 °C.[2]


  1. S.S. Wong, D.R. Bradbury, D.C. Chen, K.Y. Chiu. Elevated source/drain MOSFET. IEDM 1984. http://dx.doi.org/10.1109/IEDM.1984.190802/
  2. L. Brunet, P. Batude, C. Fenouillet-Beranger, P. Besombes, L. Hortemel, F. Ponthenier, B. Previtali, C. Tabone, A. Royer, C. Agraffeil, C. Euvrard-Colnat, A. Seignard, C. Morales, F. Fournel, L. Benaissa, T. Signamarcheix, P. Besson, M. Jourdan, R. Kachtouli, V. Benevent, J.-M. Hartmann, C. Comboroure, N. Allouti, N. Posseme, C. Vizioz, C. Arvet, S. Barnola, S. Kerdiles, L. Baud, L. Pasini, C.-M. V. Lu, F. Deprat, A. Toffoli, G. Romano, C. Guedj, V. Delaye, F. Boeuf, O. Faynot, and M. Vinet, “First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers,” 2016, pp. 1–2. Available: http://dx.doi.org/10.1109/VLSIT.2016.7573428