Sequential 3D integration 3D integration

Sequential 3D integration, also called monolithic 3D integration, refers to fabricating devices on different stacked/transferred layers sequentially on the same wafer. The stacked layers can be made of Si CMOS, high-mobility semiconductors such as Ge for p-MOS and GaAs or InP for n-MOS, and transition metal dichalcogenide (TMD) for n-MOS or p-MOS. Wide-bandgap semiconductors can also be integrated for some applications.

CMOS Processes Temperatures

The high temperatures in the CMOS processes for the upper-layer devices fabrication may damage the Cu interconnects existed on lower-layers on the wafer. The high-temperature processes include:

Backend-Compatible Transistors for Sequential 3D Integration

Backend-compatible transistors refer to a group of transistors that can be fabricated in (silicon CMOS) backend compatible processes at low temperatures. In general, the performance of the upper-layer transistors would be limited by the low process temperature requirement imposed by the bottom interconnects and often lag behind bottom CMOS transistors. Table I lists the sequential 3D integration reported in literatures.

Table I. List of reported sequential 3D integration.
Tier 1 Tier 2 Tier 3 References
Bulk Si (Pull-down transistors) poly-Si (Load PMOS) (Spike RTA activation) poly-Si (Pass NMOS) (Spike RTA activation) "S3 SRAM", Samsung, Korea[1][2]
Single-grain Si thin-film (XeCl excimer laser crystallization) Single-grain Si thin-film (XeCl excimer laser crystallization) Delft University of Technology, The Netherlands[3]
Bulk Si CMOS Amorphous Si (SRAM) Toshiba Corporation [4]
Si CMOS Nitrogen-doped AlOx RRAM Stanford University, USA[5][6]
Ge-OI p-MOS InGaAs-OI n-MOS AIST, Japan[7]
SiGe-OI p-MOS InGaAs-OI n-MOS AIST, Japan[8]
Epi-like Si (20-nm thick, laser crystallization and laser/microwave activation) Epi-like Si (20-nm thick, laser crystallization and laser/microwave activation) National Nano Device Laboratories, Taiwan[9]
SOI (UTB MOSFETs) Epi-like Ge (JL FETs and NVMs) (microwave/visible laser annealing) a-SiGeC stacked ambient light harvester National Nano Device Laboratories, Taiwan[10]
Epi-like Si on SiO2 (UTB MOSFETs) Epi-like Si (laser crystallization and CO2 laser activation) Epi-like Si (laser crystallization and CO2 laser activation) National Nano Device Laboratories, Taiwan[11]
SOI CMOS SOI CMOS "CoolCube", CEA Leti, France[12][13][14]
MoS2 n-MOS (shared gate) WSe2 p-MOS (shared gate) UC Berkeley, USA[15]
Poly-Si (logic/memory) MoS2 (transfered) (phototransistor) National Nano Device Laboratories and partners, Taiwan[16]
  • Amorphous silicon (a-Si) thin-film transistors (TFTs)
Amorphous Si Laser crystallization
Single-Grain Thin-Film Transistors
  • Single-crystal silicon thin-film transistors
Single-crystal silicon can be transfered to a wafer by wafer bonding and backside grinding/etching.
(see Semiconductor-on-Insulator)
  • Ge-on-insulator (GeOI) and III-V-on-insulator (III-V-OI) transistors
Ge based devices meet the requirement for low fabrication temperatures.
(see Semiconductor-on-Insulator and High-mobility semiconductors)
  • Carbon nanotube field effect transistors (CNFETs)
  • TMD transistors
In 2016, Chenming Hu's group reported CMOS transistors with stacked Transition metal dichalcogenide (TMD) (MoS2 and WSe2) NMOS and PMOS transistors having a shared gate.[15]
Researchers at National Nano Device Laboratories and partners, Taiwan, demonstrated a monolithic 3D image sensor by sequentially fabricating monolayer (<1nm) TMD phototransistor array by using CVD-grown MoS2 transferred onto top of a 3D logic/memory hybrid 3D IC connected by high density interconnect.[16]

3D image sensor with TMD phototransistor.png
Figure 1. (a) Schematic illustration of a monolithic 3D image sensor including (b) the top monolayer TMD phototransistor array and (c) the bottom low thermal budget 3D IC connected by high density interconnect.[16]


Monolithic 3D FPGA

In 2010, T. Naito et al. at Toshiba Corporation presented a 3D FPGA with monolithically integrated thin-film-transistor (TFT) SRAM configuration circuits over 90nm 9 layers of Cu interconnect CMOS successfully fabricated at 300mm LSI mass production line.[4]

Internet of Things


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  2. H. Lim, S.-M. Jung, Y. Rah, T. Ha, H. Park, C. Chang, W. Cho, J. Park, B. Son, J. Jeong, and others, “65nm high performance SRAM technology with 25F2 0.16μm 2 S 3 (stacked single-crystal Si) SRAM cell, and stacked peripheral SSTFT for ultra high density and high speed applications,” in Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005., 2005, pp. 549–552.
  3. M. R. Tajari Mofrad, J. Derakhshandeh, R. Ishihara, A. Baiano, J. van der Cingel, and K. Beenakker, “Stacking of Single-Grain Thin-Film Transistors,” Japanese Journal of Applied Physics, vol. 48, no. 3, p. 03B015, Mar. 2009. Available:
  4. 4.0 4.1 T. Naito, T. Ishida, T. Onoduka, M. Nishigoori, T. Nakayama, Y. Ueno, Y. Ishimoto, A. Suzuki, W. Chung, R. Madurawe, S. Wu, S. Ikeda, and H. Oyamatsu, “World’s first monolithic 3D-FPGA with TFT SRAM over 90nm 9 layer Cu CMOS,” in 2010 Symposium on VLSI Technology, 2010, pp. 219–220. Available:
  5. Y. Y. Liauw, Z. Zhang, W. Kim, A. E. Gamal, and S. S. Wong, “Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory,” in 2012 IEEE International Solid-State Circuits Conference, 2012, pp. 406–408. Available:
  6. Y. F. Yang Liauw, “Nonvolatile monolithic three-dimensional field programmable gate array with stacked resistive configuration memory,” Ph.D. dissertation, Stanford University, 2012.
  7. T. Irisawa, M. Oda, Y. Kamimuta, Y. Moriyama, K. Ikeda, E. Mieda, W. Jevasuwan, T. Maeda, O. Ichikawa, T. Osada, M. Hata, and T. Tezuka, “Demonstration of InGaAs/Ge dual channel CMOS inverters with high electron and hole mobility using staked 3D integration,” in 2013 Symposium on VLSI Technology (VLSIT), 2013, pp. T56–T57.
  8. T. Irisawa, K. Ikeda, Y. Moriyama, M. Oda, E. Mieda, T. Maeda, and T. Tezuka, “Demonstration of ultimate CMOS based on 3D stacked InGaAs-OI/SGOI wire channel MOSFETs with independent back gate,” in 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014, pp. 1–2. Available:
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  10. C. H. Shen, J. M. Shieh, W. H. Huang, T. T. Wu, C. F. Chen, M. H. Kao, C. C. Yang, C. D. Lin, H. H. Wang, T. Y. Hsieh, B. Y. Chen, G. W. Huang, M. F. Chang, and F. L. Yang, “Heterogeneously integrated sub-40nm low-power epi-like Ge/Si monolithic 3D-IC with stacked SiGeC ambient light harvester,” in 2014 IEEE International Electron Devices Meeting, 2014, p. 3.6.1-3.6.4. Available:
  11. T. T. Wu, C. H. Shen, J. M. Shieh, W. H. Huang, H. H. Wang, F. K. Hsueh, H. C. Chen, C. C. Yang, T. Y. Hsieh, B. Y. Chen, Y. S. Shiao, C. S. Yang, G. W. Huang, K. S. Li, T. J. Hsueh, C. F. Chen, W. H. Chen, F. L. Yang, M. F. Chang, and W. K. Yeh, “Low-cost and TSV-free monolithic 3D-IC with heterogeneous integration of logic, memory and sensor analogy circuitry for Internet of Things,” in 2015 IEEE International Electron Devices Meeting (IEDM), 2015, p. 25.4.1-25.4.4. Available:
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  13. P. Batude, “Three dimensional sequential integration: Study, fabrication and caracterisation,” Ph.D. dissertation (in French), Institut National Polytechnique de Grenoble - INPG, Grenoble, France, 2009.
  14. L. Brunet, P. Batude, C. Fenouillet-Beranger, P. Besombes, L. Hortemel, F. Ponthenier, B. Previtali, C. Tabone, A. Royer, C. Agraffeil, C. Euvrard-Colnat, A. Seignard, C. Morales, F. Fournel, L. Benaissa, T. Signamarcheix, P. Besson, M. Jourdan, R. Kachtouli, V. Benevent, J.-M. Hartmann, C. Comboroure, N. Allouti, N. Posseme, C. Vizioz, C. Arvet, S. Barnola, S. Kerdiles, L. Baud, L. Pasini, C.-M. V. Lu, F. Deprat, A. Toffoli, G. Romano, C. Guedj, V. Delaye, F. Boeuf, O. Faynot, and M. Vinet, “First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers,” 2016, pp. 1–2. Available:
  15. 15.0 15.1 A. B. Sachid, M. Tosun, S. B. Desai, C.-Y. Hsu, D.-H. Lien, S. R. Madhvapathy, Y.-Z. Chen, M. Hettick, J. S. Kang, Y. Zeng, J.-H. He, E. Y. Chang, Y.-L. Chueh, A. Javey, and C. Hu, “Monolithic 3D CMOS Using Layered Semiconductors,” Advanced Materials, vol. 28, no. 13, pp. 2547–2554, Apr. 2016. Available:
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