SerDes

www.3dic.org/SerDes

A SerDes (Serializer/Deserializer) is a transceiver commonly used to convert data between serial data and parallel interfaces in each direction in high speed communications. The transmitter section is a serial-to-parallel converter (Serial In Parallel Out, or SIPO), and the receiver section is a parallel-to-serial converter (Parallel In Serial Out, or PISO). Multiple SerDes interfaces are often housed in a single package. SerDes chips are used in Gigabit Ethernet systems, wireless network routers, fiber optic communications systems, FPGA [1], and storage applications (e.g., HMC).

SerDes Structure

The Figure below illustrates the basic block diagram of the transmit and receive channels of an High-Speed SerDes (HSS) device. The transmitter serializes parallel data, equalizes it, and then drives the serial data onto a differential signal pair of interconnect wires. Feed forward equalizers (FFE) are commonly used in High-Speed Serdes devices.

The receiver consists of a differential receiver, a CDR circuit which may also integrate an equalizer, and deserializes the data based upon the sample point established by the CDR. Peaking amplifiers and/or decision feedback equalizers (DFE) are commonly used for equalization in High-Speed Serdes receiver devices.

Basic block diagram of typical high-speed SerDes.png
Basic block diagram of typical high-speed serdes

Equalization for High-Speed SerDes

Signal integrity concerns frequently dictate that the data signal be equalized at the transmitter and/or receiver in order to counter the effects of the channel and decode the signal properly.

Feed-Forward Equalization (FFE)

Continuous Time Linear Equalizer (CTLE)

Desision Feadback Equalizer (DFE)

Electrical and Optical SerDes

Books

  1. D. R. Stauffer, Ed., High speed serdes devices and applications. New York: Springer, 2008.

References

  1. N. Kim, D. Wu, J. Carrel, J.-H. Kim, and P. Wu, “Channel design methodology for 28Gb/s SerDes FPGA applications with stacked silicon interconnect technology,” in Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd, 2012, pp. 1786–1793. Available: http://dx.doi.org/10.1109/ECTC.2012.6249080