Single-grain thin-film transistors

www.3dic.org/Single-grain thin-film transistors

The single-grain thin-film transistors (SG TFTs) are aimed at obtaining characteristics comparable to silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS), by placing the channel of a TFT inside a single grain. Single-grain location-controlled silicon is obtained by the so-called μ-Czochrolski process using excimer laser. In this method the position of the grains is controlled and the channel of the TFTs are designed to fit inside a grain-boundary-less area. The single-grain TFTs can be stacked sequentially to fabricate 3D IC.

Single-grain Si thin-film transistors

Starting layer Channel crystallization Channel dopant activation Source/Drain dopant activation Ref
a-Si (LPCVD at 545 °C) Pulsed XeCl excimer laser (308 nm) During the crystallization Excimer laser annealing (ELA) [1]

Single-grain Ge thin-film transistors

References

  1. M. R. Tajari Mofrad, J. Derakhshandeh, R. Ishihara, A. Baiano, J. van der Cingel, and K. Beenakker, “Stacking of Single-Grain Thin-Film Transistors,” Japanese Journal of Applied Physics, vol. 48, no. 3, p. 03B015, Mar. 2009. Available: http://dx.doi.org/10.1143/JJAP.48.03B015