Through-oxide vias (TOV)

www.3dic.org/TOV

Through-oxide vias (TOV), or called 3D-vias, are vertical electrical connection (via) passing through a oxide layer, fabricated after oxide-to-oxide wafer bonding (i.e., postbonding via-last process) and completely removing backside silicon. It is smaller to but shorter than the TSV, and comparable to the SuperContacts. TOV was developed by researchers at IBM Thomas J. Watson Res. Center (through face-to-back bonding)[1], MIT Lincoln Laboratory (through face-to-face bonding) [2], and other groups.

3D ICs using TOV

In 2005, V. Suntharalingam et al. of MIT, Lincoln Laboratories presented stacked 3D integration of CMOS image sensor (CIS) on Si readout circuits by oxide-oxide bonding and TOV [2].

In 2011, C.L. Chen et al. presented a wafer-scale three dimensional (3D) integration technique hybridize InP-based photodiode arrays with Si readout circuits by wafer bonding and TOV.[3] The infrared (IR) photodiodes consisted of an InGaAs absorption layer grown on the InP substrate and were fabricated in the same processing line as SOI readout circuits to allow 3D integration in the Si fabrication facility. The finished 150-mm-diameter InP wafer was directly bonded to the SOI wafer and interconnected to the Si readout circuits by the TOV. A 32 × 32 array with 6-μm pixel size was demonstrated. The 3D integration of InP with Si wafers achieved the smallest pixel size, which is less than a half of that can be achieved using conventional flip-chip bump bonding technique.

References

  1. A. W. Topol, B. K. Furman, K. W. Guarini, L. Shi, G. M. Cohen, and G. F. Walker, “Enabling technologies for wafer-level bonding of 3D MEMS and integrated circuit structures,” in 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546), 2004, vol. 1, p. 931–938 Vol.1. Available: http://dx.doi.org/10.1109/ECTC.2004.1319449
  2. 2.0 2.1 V. Suntharalingam, R. Berger, J. A. Burns, C. K. Chen, C. L. Keast, J. M. Knecht, R. D. Lambert, K. L. Newcomb, D. M. O’Mara, D. D. Rathman, D. C. Shaver, A. M. Soares, C. N. Stevenson, B. M. Tyrrell, K. Warner, B. D. Wheeler, D.-R. W. Yost, and D. J. Young, “Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology,” in Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International, 2005, p. 356–357 Vol. 1. Available: http://dx.doi.org/10.1109/ISSCC.2005.1494016
  3. C. L. Chen, D.-R. Yost, J. M. Knecht, J. Wey, D. C. Chapman, D. C. Oakley, A. M. Soares, L. J. Mahoney, J. P. Donnelly, C. K. Chen, V. Suntharalingam, R. Berger, W. Hu, B. D. Wheeler, C. L. Keast, and D. C. Shaver, “Wafer-scale 3D integration of InGaAs photodiode arrays with Si readout circuits by oxide bonding and through-oxide vias,” Microelectronic Engineering, vol. 88, no. 1, pp. 131–134, Jan. 2011. Available: http://dx.doi.org/10.1016/j.mee.2010.09.020