TSMC-SoIC (System-on-Integrated-Chips) is a front-end 3D chip bump-less stacking technology proposed by TSMC, which integrates heterogeneous chips (Known Good Die, KGD), including logic ICs and memory (like 3D-SRAM), that are fabricated on different process nodes onto a single chip stack in front-end of line for a subsequent packaging process. The SoIC solution enables known good dies of different sizes, process technologies, and materials to be directly stacked together. Compared to typical 3DIC solutions with micro-bumps, TSMC’s SoIC delivers higher bump density and speed, while consuming much less power. What’s more, SoIC is a “front-end” integration solution connecting two or more dies before they are packaged. Therefore, a SoIC stack can be further integrated with other SoIC or chips in one of TSMC’s “back-end” advanced packaging technologies such as InFO or CoWoS, offering a powerful “3D-by-3D” system-level solution.
TSMC announced the SoIC technology is 2018. TSMC estimates that in 2021 their SoIC technology will go into mass production.
TSMC showcased its true 3D integration technology with the paper “3D Multi-chip Integration with System on Integrated Chips (SoIC)” at the 2019 Symposia on VLSI Technology & Circuits held June 9-14th 2019 in Kyoto, Japan.
- WoW (Wafer-on-Wafer): refers to using wafer-on-wafer stacking to build 3D chip stacks using bumpless wafer bonding.
- CoWoS (Chip-on-Wafer-on-Substrate): TSMC’s 2.5D interposer technology
- InFO(Integrated Fan-out): TSMCs integrated fan-out technology and claims to be the first high-density 2D/3D fan-out wafer level package (FOWLP).
- Front-end 3D (FE 3D) refers to using front-end processes to build 3D chip stacks using bumpless wafer bonding. FE 3D eliminates the need for micro bumps.
- Back-end 3D (BE 3D) refers to traditional 3D stacking that uses conventional through silicon via (TSV) interconnects, polymers, molding compounds, copper pillars, and micro-bumping.