TSV keep-out zone

www.3dic.org/TSV keep-out zone

TSV keep-out zone (KOZ) is the area that devices (like transistors and Si ring resonators) being impacted by the TSV-induced stress and coupling noise.

Introduction

TSV KOZ induced by stress

Thermal stresses induced in the TSV structures can affect the device performance by degrading carrier mobility. A criterion of 5% change in the carrier mobility is typically used to estimate the the dimension of the KOZ. The effect of stress interaction depends on the filling material, the ratio of pitch to diameter of the TSV array, etc.

TSV KOZ induced by coupling noise

TSVs introduce an important source of coupling noise arising from electromagnetic (EM) coupling between TSVs and the active regions. The electrical noise coupling from the TSVs to the body voltage of MOSFET devices (which can change the threshold voltage) is crucial for analog and low- noise-tolerant circuits. A typical range of the noise coupling from fast-switching digital signals to noise-sensitive analog circuits is −35 to −80 dB.

C. Xu et al. developed compact models for dual-well bulk CMOS (also valid for the case of the FD-SOI on thin BOX) and the models are employed for estimating the keey-out radius from the center of the TSVs to the active regions to minimize the impact of such coupling noise.[1][2]

For evaluation of TSV-FinFET noise coupling, B. Gaynor et al. developed a simulation methodology by accurately modeling substrate noise due to digital signals on nearby TSVs and improving the extraction of substrate circuit models from full-wave electromagnetic simulations.[3][4]

References

  1. C. Xu, R. Suaya, and K. Banerjee, “Compact modeling and analysis of coupling noise induced by through-Si-vias in 3-D ICs,” in Electron Devices Meeting (IEDM), 2010 IEEE International, 2010, p. 8.1.1-8.1.4. Available: http://dx.doi.org/10.1109/IEDM.2010.5703319
  2. C. Xu, R. Suaya, and K. Banerjee, “Compact Modeling and Analysis of Through-Si-Via-Induced Electrical Noise Coupling in Three-Dimensional ICs,” IEEE Transactions on Electron Devices, vol. 58, no. 11, pp. 4024–4034, Nov. 2011. Available: http://dx.doi.org/10.1109/TED.2011.2166156
  3. B. Gaynor, “Simulation of FinFET Electrical Performance Dependence on Fin Shape and TSV and Back-Gate Noise Coupling in 3-D Integrated Circuits,” Ph.D., Tufts University, US, 2014.
  4. B. D. Gaynor and S. Hassoun, “Simulation Methodology and Evaluation of Through Silicon Via (TSV)-FinFET Noise Coupling in 3-D Integrated Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 8, pp. 1499–1507, Aug. 2015. Available: http://dx.doi.org/10.1109/TVLSI.2014.2341834