- JESD229: Wide I/O Mobile DRAM was published in Dec 2011 by JEDEC JC-42.6;
- JESD229-2: WIDE I/O 2 (WideIO2) was published in Aug 2014.
SDR Wide I/O 1
The 2 Gb single data rate (SDR) Wide I/O 1 DRAM having 4 channels with 512 I/O pins, developed by Samsung, was using 50 nm technology and stacking of two 1-Gb dies with TSVs and microbumps. The TSVs have with a 7.5-μm diameter and 40-μm pitch. There are 46 x 6 microbump pads per channel, with 20-μm x 17-μm size and 50-μm x 40-μm pitch. 
A single 1 Gb Wide I/O DRAM exhibits 330.6 mW read operating power during 4 channel operation (at 200 MHz), achieving 12.8 GB/s data bandwidth, which is 8 times data bandwidth compared to LPDDR and 4 times compared to LPDDR2, because of its 512 I/O pins. The measured I/O power per 1 bit data (power/bandwidth), is only 0.78 mW/Gbps, which corresponds to 4.5% of LPDDR’s. Reduction of I/O power comes from voltage and I/O loading reduction together with data bandwidth increase.
Comparing the 2-chip stacked Wide I/O DRAM to the single one, standby power is a simple sum of 2 devices, but DQ power increases about 1.5 because of output loading increase. Total power increases 14%.
Samsung’s Wide IO.
STATS ChipPAC and UMC's Wide IO stacked on a TSV-embedded 28nm processor test chip.
DDR Wide I/O 2
The Wide I/O 2 DRAM developed by SK Hynix has 512 I/Os, which is the same as the SDR Wide I/O DRAM, but by using double data rate (DDR) and operating at 1066Mb/s, its bandwidth achieves 68.2 GB/s, which is quadrupled compared to LPDDR4 (single-die comparison). Moreover, since Wide I/O 2 DRAM is stacked in a 3D structure with the DRAM controller (SiP type), the input/output capacitance (CIO) is decreased and a power efficiency of 28 mW/GB/s (3.5 mW/Gbps) in READ operation mode is achieved.
|Wide I/O 1||Wide I/O 2|
|Channel||4 channel||8 channel|
|Operating Supply Voltage||1.2 V||1.1 V|
|Bandwith (single die)||12.8 GB/s||68.2 GB/s (1066 Mb/s x 512 I/Os)|
|I/O power per bit (READ mode, single die)||0.78 mW/Gbps||3.5 mW/Gbps|
|Capacity||1 Gb to 2 Gb||8 Gb to 32 Gb|
|Microbump||20-μm x 17-μm size||20 μm in diameter|
|TSVs||7.5-μm diameter, 40-μm pitch|
See main article 3D-SWIFT.
Zhang et al. reorganized the Wide I/O DRAM core in their proposed 3-D SWIFT architecture, which employs a large number of small banks to enable greater bank-level parallelism.
See main article 3-D WiRED.
3-D WiRED is a optimized Wide I/O DRAM architecture, aiming to reduce access latency and energy consumption.
- JESD229, WIDE I/O SINGLE DATA RATE (WIDE I/O SDR), https://www.jedec.org/standards-documents/docs/jesd229
- JESD229-2, WIDE I/O 2 (WideIO2), https://www.jedec.org/standards-documents/docs/jesd229-2
- Jung-Sik Kim, Chi Sung Oh, Hocheol Lee, Donghyuk Lee, Hyong Ryol Hwang, Sooman Hwang, Byongwook Na, Joungwook Moon, Jin-Guk Kim, Hanna Park, Jang-Woo Ryu, Kiwon Park, Sang Kyu Kang, So-Young Kim, Hoyoung Kim, Jong-Min Bang, Hyunyoon Cho, Minsoo Jang, Cheolmin Han, Jung-Bae Lee, Joo Sun Choi, and Young-Hyun Jun, “A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4x128 I/Os Using TSV Based Stacking,” IEEE Journal of Solid-State Circuits, vol. 47, no. 1, pp. 107–116, Jan. 2012. Available: http://dx.doi.org/10.1109/JSSC.2011.2164731
- Y. J. Yoon, B. D. Jeon, B. S. Kim, K. U. Kim, T. Y. Lee, N. Kwak, W. Y. Shin, N. Y. Kim, Y. Hong, K. P. Kang, D. Y. Ka, S. J. Lee, Y. S. Kim, Y. K. Noh, J. Kim, D. K. Kang, H. U. Song, H. G. Kim, and J. Oh, “An 1.1V 68.2GB/s 8Gb Wide-IO2 DRAM with non-contact microbump I/O test scheme,” in 2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, pp. 320–322. Available: http://dx.doi.org/10.1109/ISSCC.2016.7418036
- T. Zhang, C. Xu, K. Chen, G. Sun, and Y. Xie, “3D-SWIFT: a high-performance 3D-stacked wide IO DRAM,” (Best Paper Award) in ACM Great Lakes Symposium on VLSI, 2014, pp. 51–56, Houston, TX. Available: http://dx.doi.org/10.1145/2591513.2591529